Flash memory is an electronic (solid-state) non-volatile computer storage medium that can be electrically erased and reprogrammed. The NAND flash memory is a main type of flash memory named after the NAND logic gates, it has advantages of fast programming and short erasing time.
In order to communicate with an external control device (such as a computer), an interface of the NAND flash memory is needed. The interface in NAND flash memory mainly comprises seven control signals except for I/O bus:    1, CE# (Chip Enable), if there is no CE signal is detected, NAND flash memory will stay in a standby mode without responding to any control signal.    2, WE# (Write Enable), it writes the data, address or command to the NAND flash memory.    3, RE# (Read Enable), it provides a buffer for output data.    4, CLE (Command Latch Enable), in the case of CLE is in high level, when a rising edge of WE# is detected, command is latched in a NAND command register.    5, ALE (Address Latch Enable), in the case of ALE is in high level, when a rising edge of WE# is detected, address is latched in a NAND address register.    6, R/B# (Ready/Busy), if NAND flash memory is busy, the R/B# is toggled to low level, a pull-up resistor is needed.    7, WP#: Write Protect)—prevent unexpected command write operation.
In the conventional technology, as shown in FIG. 1, if it is required to output current status of a NAND flash memory, a controller of the NAND flash memory needs to perform the following processes:    1, in the first clock cycle, in the situation of ALE signal to be 0, the CLE signal is toggled to be 1, such as in time t1 of FIG. 1.    2, the WE# signal is toggled to be 0 by the NAND controller in time t2 of FIG. 1, and at the same time the read status command 70h is issued via the I/O bus.    3, in the second clock cycle, the RE# signal is toggled to be 0 in time t3 of FIG. 1, as long as the falling edge of the RE# is detected, a status signal is issued via the I/O bus. The external controller such as the computer may obtain the status of NAND flash memory via the I/O bus.
According to the above processes, if the external controller needs to know the current status of the NAND flash memory, a data (0×70) should be write in the NAND flash memory, therefore the WE# signal should be set to 0 in advance to write the data in. After writing the data in, the WE# signal is set to 1 to close the data receiving channel. The read status command 70h is defined by ONFI standard, which is not illustrated herein for concise.
In the conventional technology, the two-clock-cycle waiting time is needed once the external controller needs to know the status, which consumes time and lowers the system performance. As a person skilled in the art can understand, acquiring the status of the NAND flash memory is very often used in operating the NAND flash memory, the command of acquiring the status signal is needed each time after other commands such as programming or erasing are sent. Therefore the speed for waiting for status signal should be improved.